designed primarily for use with high-voltage vacuum-fluorescent displays, the ucn5815a and ucn5815ep bimos ii integrated circuits consist of eight npn darlington source drivers with output pull- down resistors, a cmos latch for each driver, and common strobe, blanking, and enable functions. bimos ii devices have considerably better data-input rates than the original bimos circuits. with a 5 v logic supply, they will operate to at least 4.4 mhz. with a 12 v supply, significantly higher speeds are obtained. the cmos inputs cause minimum loading and are compatible with standard cmos and nmos logic commonly found in microprocessor designs. ttl circuits may require the use of appropri- ate pull-up resistors. the bipolar outputs may be used as segment, dot (matrix), bar, or digit drivers in vacuum-fluorescent displays. all eight outputs can be activated simultaneously at ambient temperatures in excess of 75 c. to simplify printed wiring board layout, output connections are opposite the inputs. a minimum component display subsystem, requiring few or no discrete components, can be assembled using the ucn5815a/ep with the ucn5810af/epf/lwf, ucn5812af/epf, or ucn5818af/epf serial-to-parallel latched drivers. suffix ??devices are furnished in a standard 22-pin plastic dip; suffix ?p?indicates a 28-lead plcc. bimos ii 8-bit latched source drivers ucn5815a features to 4.4 mhz date-lnput rate high-voltage source outputs cmos, nmos, ttl compatible inputs low-power cmos latches internal pull-down resistors wide supply-voltage range always order by complete part number: part number package ucn5815a 22-pin dip ucn5815ep 28-lead plcc absolute maximum ratings at +25 c free-air temperature output voltage, v out . . . . . . . . . . . . . . 60 v logic supply voltage range, v dd . . . . . . . . . . . . . . . . . . 4.5 v to 15 v load supply voltage range, v bb . . . . . . . . . . . . . . . . . . 5.0 v to 60 v input voltage range, v in . . . . . . . . . . . -0.3 v to v dd + 0.3 v continuous output current, i out . . . . . . . . . . . . . . . . . . . . . . -40 ma package power dissipation, p d (ucn5815a) . . . . . . . . . . . . . . . 2.5 w* (ucn5815ep) . . . . . . . . . . . . . 2.27 w* operating temperature range, t a . . . . . . . . . . . . . . . . . -20 c to +85 c storage temperature range, t s . . . . . . . . . . . . . . . . -55 c to +150 c * derate linearly to 0 w at +150 c. caution: cmos devices have input static protection but are susceptible to damage when exposed to extremely high static electrical charges. data sheet 26183.10a* 5815 221 22 logic supply enable 1 blanking strobe v dd 3 4 5 6 7 16 17 18 19 20 out 1 out 2 out 3 out 4 in 1 in 2 in 3 in 4 7 8 9 10 11 12 13 14 15 ground out 5 out 6 out 7 dwg. pp-015-3 out 8 load supply in 5 in 6 in 7 in 8 latches v bb
5815 bimos ii 8-bit latched source drivers 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 electrical characteristics at t a = +25 c, v bb = 60 v, v dd = 5 v and 12 v (unless otherwise noted). limits characteristic symbol test conditions min. max. units output off voltage v out 1.0 v output on voltage v out i out = -25 ma, v bb = 60 v 57.5 v output pull-down current i out v out = v bb 400 850 a output leakage current i out t a = 70 c -15 a input voltage v in(1) v dd = 5.0 v 3.5 5.3 v v dd = 12 v 10.5 12.3 v v in(0) -0.3 +0.8 v input current i in(1) v dd = v in = 5.0 v 100 a v dd = v in = 12 v 240 a input lmpedance z in v dd = 5.0 v 50 k ? supply current l bb all outputs on, all outputs open 10.5 ma all outputs off, all outputs open 100 a l dd v dd = 5.0 v, all outputs off, all inputs = 0 v 100 a v dd = 12 v, all outputs off, all inputs = 0 v 200 a v dd = 5.0 v, one output on, all inputs = 0 v 1.0 ma v dd = 12 v, one output on, all inputs = 0 v 3.0 ma note: positive (negative) current is defined as going into (coming out of) the specified device pin. typical input circuit typical output driver in v dd dwg. no. ep-010-4a dwg. no. ep-021-3 out 100 k v bb copyright ? 1984, 2000 allegro microsystems, inc.
5815 bimos ii 8-bit latched source drivers ucn5815ep dwg. no. a-14,357 information present at an input is trans- ferred to its latch when the strobe and enable are high. the latches will continue to accept new data as long as both strobe and enable are held high. with either strobe or enable in the low state, no information can be loaded into the latches. when the blanking input is high, all of the output buffers are disabled (off) without affecting the information stored in the latches. with the blanking input low, the outputs are controlled by the state of the latches. dwg. no. a-10,991 timing conditions (v dd = 5 v, t a = +25 c, logic levels are v dd and ground) a. minimum data active time before strobe enabled (data set-up time) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 ns b. minimum data active time after strobe disabled (data hold time) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 ns c. minimum strobe pulse width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 ns d. typical time between strobe activation and output on to off transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.0 s e. typical time between strobe activation and output off to on transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 ns f. minimum data pulse width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 ns inputs out n in n strobe enable blank t-1 t 0110x0 1110x1 xx x 1 x0 x0 x 0 11 x0 x 0 00 xx 0 0 11 xx 0 0 00 x = irrelevant t-1 = previous output state t = present output state truth table timing is representative of a 4.4 mhz data input rate. higher speeds may be attainable with increased supply voltage; operation at high temperatures will reduce the specified maximum clock frequency.
5815 bimos ii 8-bit latched source drivers 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 ucn5815a dimensions in inches (cvontrolling dimensions) dimensions in millimeters (for reference only) notes: 1. exact body and lead configuration at vendor s option within limits shown. 2. lead spacing tolerance is non-cumulative. 3. lead thickness is measured at seating plane or below. 4. supplied in standard sticks/tubes of 17 devices. 22 12 3 11 0.380 0.330 0.210 max 0.070 0.030 0.015 min 0.022 0.014 0.100 bsc 0.005 min 0.160 0.115 0.015 0.008 0.400 bsc dwg. ma-002-22 in 0.500 max 12 1.120 1.050 22 12 3 11 9.65 8.39 5.33 max 0.070 0.030 28.44 26.67 0.39 min 0.558 0.356 2.54 bsc 0.13 min 4.06 2.93 0.381 0.204 10.16 bsc dwg. ma-002-22 mm 12.70 max 12
5815 bimos ii 8-bit latched source drivers ucn5815ep dimensions in inches (controlling dimensions notes: 1. exact body and lead configuration at vendor s option within limits shown. 2. lead spacing tolerance is non-cumulative. 3. supplied in standard sticks/tubes of 38 devices or add tr to part number for tape and reel. dimensions in millimeters (for reference only) 18 12 0.020 min 0.050 bsc 1 28 index area dwg. ma-005-28a in 0.026 0.032 0.013 0.021 26 25 19 11 4 5 0.165 0.180 0.495 0.485 0.456 0.450 0.495 0.485 0.456 0.450 0.219 0.191 0.219 0.191 0.51 min 4.57 4.20 1.27 bsc 12.57 12.32 11.582 11.430 1 28 index area dwg. ma-005-28a mm 0.812 0.661 0.331 0.533 12.57 12.32 26 25 19 18 12 11 4 5 11.58 11.43 5.56 4.85 5.56 4.85
5815 bimos ii 8-bit latched source drivers 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 power interface drivers function output ratings* part number ? serial-input latched drivers 8-bit (saturated drivers) -120 ma 50 v? 5895 8-bit 350 ma 50 v 5821 8-bit 350 ma 80 v 5822 8-bit 350 ma 50 v? 5841 8-bit 350 ma 80 v? 5842 8-bit (constant-current led driver) 75 ma 17 v 6275 8-bit (dmos drivers) 250 ma 50 v 6595 8-bit (dmos drivers) 350 ma 50 v? 6a595 8-bit (dmos drivers) 100 ma 50 v 6b595 10-bit (active pull-downs) -25 ma 60 v 5810-f and 6809/10 12-bit (active pull-downs) -25 ma 60 v 5811 and 6811 16-bit (constant-current led driver) 75 ma 17 v 6276 20-bit (active pull-downs) -25 ma 60 v 5812-f and 6812 32-bit (active pull-downs) -25 ma 60 v 5818-f and 6818 32-bit 100 ma 30 v 5833 32-bit (saturated drivers) 100 ma 40 v 5832 parallel-input latched drivers 4-bit 350 ma 50 v? 5800 8-bit -25 ma 60 v 5815 8-bit 350 ma 50 v? 5801 8-bit (dmos drivers) 100 ma 50 v 6b273 8-bit (dmos drivers) 250 ma 50 v 6273 special-purpose devices unipolar stepper motor translator/driver 1.25 a 50 v? 5804 addressable 8-bit decoder/dmos driver 250 ma 50 v 6259 addressable 8-bit decoder/dmos driver 350 ma 50 v? 6a259 addressable 8-bit decoder/dmos driver 100 ma 50 v 6b259 addressable 28-line decoder/driver 450 ma 30 v 6817 * current is maximum specified test condition, voltage is maximum rating. see specification for sustaining voltage limits. negative current is defined as coming out of (sourcing) the output. ? complete part number includes additional characters to indicate operating temperature range and package style. internal transient-suppression diodes included for inductive-load protection.
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